The present application relates to semiconductor structures and methods of forming the same. More particularly, the present application relates to an engineered substrate containing a strained silicon material layer portion located on one region of a relaxed silicon material layer and a relaxed silicon material portion located on another region of the relaxed silicon material layer. The present application also relates to a semiconductor structure that contains one semiconductor device located at least partially on the strained silicon material player portion and another semiconductor device located at least partially on the relaxed silicon material portion. The present application also provides various methods for forming the aforementioned engineered substrate and the aforementioned semiconductor structure.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that MOSFETs are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
In one example, and as CMOS technology is pushed to smaller device pitch, conventional strain engineering methods such as, for example, stress liners or embedded stressors are beginning to run out of steam. Substrate strain engineering is however independent of device pitch and thus has gained importance in the semiconductor industry.
Biaxially strained silicon with tensile silicon is known to benefit n-type field effect transistors (i.e., nFETs). Device data on bulk substrates, partially depleted semiconductor-on-insulator (SOI) substrates, extremely thin SOI substrates and non-planar substrates, i.e., semiconductor fins, show increased nFET performance on both strained silicon on silicon germanium or on a strained silicon germanium donor on insulator (SSDOI) substrate. One advantage of SSDOI substrates is that the donor silicon germanium layer can be reused to reduce cost due to lengthy silicon germanium epitaxy. Direct bonding of strained silicon on a relaxed silicon substrate is known, but leads to a defect interface that acts as a leakage path. As such, there is a continued need for providing engineered substrates that avoid the problems mentioned above.